1. Field of the Invention
The present invention relates to a probe pin for testing electric characteristics of an apparatus, such as a semiconductor integrated circuit, an LCD, a magnetic recording device, or the like, and to a method for fabricating the probe pin. The invention also relates to a probe card using a set of probe pins.
2. Description of the Related Art
A test probe or a probe card is generally used to test the electric characteristics of a semiconductor integrated circuit printed on a wafer before the wafer is cut into chips. As the pattern of a semiconductor integrated circuit becomes fine and dense, the pitch of the probe pins have to be reduced. A fine-pitch probe can be fabricated by, for example, forming a silicon single crystal pin by a VLS (vapor liquid solid) technique (R. S. Wangner and W. C. Ellis, Appl. Phys. Lett. 4, 1996 at 89). In this technique, a metal, for example, gold (Au) is placed on a substrate, and this metal is heated in the gas phase containing the composition of the probe (that is, silicon). Then, silicon is deposited in the solid phase via the molten metal in the alloy liquid phase. This method allows a silicon single crystal probe to be formed easily and accurately at a fine pitch making use of crystal growth. Because a single crystal silicon probe has a high electric resistance, the silicon probe is generally coated with a low resistance metal, such as gold.
FIG. 1 illustrates a conventional silicon probe 100. The silicon probe 100 has pin core 102a rising in the vertical direction, a silicon wiring layer 102b extending in the horizontal direction, a nickel-phosphorus seed layer 103, and a gold (Au) plating layer 104 covering the seed layer 103. The vertical pin core 102a, the seed layer 103, and the plating layer 104 form an individual test pin 105. On the other hand, the horizontal wising layer 102b, the seed layer 103, and the plating layer 104, form a lead electrode 106 for extracting an electrode from the test probe 105. The test pin 105 is connected to an external circuit (for example, a tester) via the lead electrode 106.
To fabricate the conventional test probe shown in FIG. 1, a wiring pattern corresponding to the lead electrode 106 must be formed prior to forming the single crystal silicon pin rising in the vertical direction. The wiring pattern can be formed by, for example, forming a silicon layer on a sapphire substrate 101, coating the sapphire substrate with a photoresist, patterning the photoresist into a horizontal wiring pattern, and etching the silicon layer into the lead using the photoresist as a mask.
However, the conventional silicon probe requires a certain space around each pin in order to extract and arrange the lead on the substrate. In addition, each lead extending from the associated pin must be arranged at a certain distance from the other leads, so that signals propagating through adjacent leads will not interfere each other. These factors greatly limit the freedom of producing two-dimensional layout of a probe, especially with respects to the positions and the density of the probe pins. This limitation is a fatal obstacle to producing a fine-pitch probe for testing a highly dense circuit.
Another problem in the conventional probe set is that if the leads from the associated probes are arranged in the two-dimensional manner, the wiring length becomes inevitably long, and in addition, the lengths of the leads extending from different probes differ from one another. Consequently, variation occurs in signal transfer among different leads when measuring electric characteristics at a high frequency. The long lead causes the contact resistance to increase between the probe pin and the electrode formed on the substrate, which results in a measurement error.